A semiconductor integrated circuit (IC) is manufactured using a multi-phase process involving photographic and chemical process steps. In general, common phases in fabricating an IC can include, but are not limited to, front-end-of-line (FEOL) processing, back-end-of-line (BEOL) processing, wafer testing, die preparation, and packaging. FEOL processing generally refers to the formation of circuit elements such as transistors. BEOL processing generally refers to the formation of metal layers and interconnects. Wafer testing or wafer sort generally refers to functional testing that can be performed on dies while still in wafer form. Die preparation generally refers to preparatory steps applied to dies for packaging. Finally, packaging generally refers to the process of mounting or placing dies within plastic, ceramic, or other packages that facilitates use of the IC within another system, e.g., upon a circuit board.
Typically, ICs are characterized in terms of performance. Performance can be measured in terms of whether the IC is able to perform within established design requirements relating, for example, to operating frequency, signal fidelity, signal response, or the like. Each IC can be classified into one of a plurality of different “bins,” where each bin refers to a particular range of performance typically within the design requirements. Each IC can be priced and sold according to the particular bin to which the IC is classified. Performance analysis also facilitates the identification of ICs that do not meet minimum design requirements.
In some cases, a wire formed within an IC can be viewed as functional in that the wire passes a signal, but exhibits other types of defects. The wire, for example, may not appear as an open circuit when tested. Despite the passage of signal, the defects present in the wire may cause the wire to fail to meet design requirements. For example, when tested the wire may have a resistance that is too high or out of tolerance when compared with established design requirements for the IC. In another example, the wire may exhibit delay characteristics that are too large or out of tolerance when compared with established design requirements for the IC.